nios2Qsys

2014.09.26.23:17:31 Datasheet
Overview
  clk_0  nios2Qsys
   HEX3TO0PIO
 out_port  
 out_port  
 rxd  
 txd  
 cts_n  
 rts_n  
 out_port  
 in_port  
 bidir_port  
 bidir_port  
Processor
   CPU Nios II 12.0
All Components
   Onchip_Memory256KB altera_avalon_onchip_memory2 12.0
   CPU altera_nios2_qsys 12.0
   sysid altera_avalon_sysid_qsys 12.0
   systimer altera_avalon_timer 12.0
   HEX3TO0PIO altera_avalon_pio 12.0
   character_lcd_0 altera_up_avalon_character_lcd 12.0
   HEX7TO4PIO altera_avalon_pio 12.0
   jtag_uart_0 altera_avalon_jtag_uart 12.0
   rs232_uart_0 altera_avalon_uart 12.0
   sdram128MB altera_avalon_new_sdram_controller 12.0
   sd_clk altera_avalon_pio 12.0
   sd_wp_n altera_avalon_pio 12.0
   sd_cmd altera_avalon_pio 12.0
   sd_dat altera_avalon_pio 12.0
Memory Map
CPU
 data_master  instruction_master
  Onchip_Memory256KB
s1  0x08040000 0x08040000
  CPU
jtag_debug_module  0x08080800 0x08080800
  sysid
control_slave  0x080810a0
  systimer
s1  0x08081000
  HEX3TO0PIO
s1  0x08081040
  character_lcd_0
avalon_lcd_slave  0x080810b0
  HEX7TO4PIO
s1  0x08081050
  jtag_uart_0
avalon_jtag_slave  0x080810a8
  rs232_uart_0
s1  0x08081020
  sdram128MB
s1  0x00000000
  sd_clk
s1  0x08081060
  sd_wp_n
s1  0x08081070
  sd_cmd
s1  0x08081080
  sd_dat
s1  0x08081090

clk_0

clock_source v12.0


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

Onchip_Memory256KB

altera_avalon_onchip_memory2 v12.0
CPU data_master   Onchip_Memory256KB
  s1
instruction_master  
  s1
jtag_debug_module_reset  
  reset1
Clock_Signals sys_clk  
  clk1
sys_clk_reset  
  reset1
clk_0 clk_reset  
  reset1


Parameters

allowInSystemMemoryContentEditor false
autoInitializationFileName nios2Qsys_Onchip_Memory256KB
blockType AUTO
dataWidth 32
deviceFamily CYCLONEIVE
dualPort false
initMemContent true
initializationFileName Onchip_Memory256KB
instanceID NONE
memorySize 262144
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
simMemInitOnlyFilename 0
singleClockOperation false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
generateLegacySim false
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "Onchip_Memory256KB"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "Automatic"
WRITABLE 1
DUAL_PORT 0
SINGLE_CLOCK_OP 0
SIZE_VALUE 262144u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "Auto"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

CPU

altera_nios2_qsys v12.0
clk_0 clk_reset   CPU
  reset_n
Clock_Signals sys_clk  
  clk
sys_clk_reset  
  reset_n
data_master   Onchip_Memory256KB
  s1
instruction_master  
  s1
jtag_debug_module_reset  
  reset1
jtag_debug_module_reset   Clock_Signals
  clk_in_primary_reset
data_master   sysid
  control_slave
jtag_debug_module_reset  
  reset
data_master   systimer
  s1
d_irq  
  irq
jtag_debug_module_reset  
  reset
data_master   HEX3TO0PIO
  s1
jtag_debug_module_reset  
  reset
data_master   character_lcd_0
  avalon_lcd_slave
jtag_debug_module_reset  
  clock_reset_reset
data_master   HEX7TO4PIO
  s1
jtag_debug_module_reset  
  reset
data_master   jtag_uart_0
  avalon_jtag_slave
d_irq  
  irq
jtag_debug_module_reset  
  reset
data_master   rs232_uart_0
  s1
d_irq  
  irq
jtag_debug_module_reset  
  reset
data_master   sdram128MB
  s1
jtag_debug_module_reset  
  reset
data_master   sd_clk
  s1
data_master   sd_wp_n
  s1
data_master   sd_cmd
  s1
data_master   sd_dat
  s1


Parameters

setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_bit31BypassDCache true
setting_bigEndian false
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTestEndChecker false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
muldiv_divider false
mpu_useLimit false
mpu_enabled false
mmu_enabled false
mmu_autoAssignTlbPtrSz true
manuallyAssignCpuID false
debug_triggerArming true
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
dcache_omitDataMaster false
cpuReset false
is_hardcopy_compatible false
setting_shadowRegisterSets 0
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mmu_TLBMissExcOffset 0
debug_jtagInstanceID 0
resetOffset 0
exceptionOffset 32
cpuID 0
cpuID_stored 0
breakOffset 32
userDefinedSettings
resetSlave Onchip_Memory256KB.s1
mmu_TLBMissExcSlave
exceptionSlave Onchip_Memory256KB.s1
breakSlave CPU.jtag_debug_module
setting_perfCounterWidth 32
setting_interruptControllerType Internal
setting_branchPredictionType Automatic
setting_bhtPtrSz 8
muldiv_multiplierType EmbeddedMulFast
mpu_minInstRegionSize 12
mpu_minDataRegionSize 12
mmu_uitlbNumEntries 4
mmu_udtlbNumEntries 6
mmu_tlbPtrSz 7
mmu_tlbNumWays 16
mmu_processIDNumBits 8
impl Fast
icache_size 4096
icache_ramBlockType Automatic
icache_numTCIM 0
icache_burstType None
dcache_bursts false
debug_level Level1
debug_OCIOnchipTrace _128
dcache_size 2048
dcache_ramBlockType Automatic
dcache_numTCDM 0
dcache_lineSize 32
resetAbsoluteAddr 134479872
exceptionAbsoluteAddr 134479904
breakAbsoluteAddr 134744096
mmu_TLBMissExcAbsAddr 0
instAddrWidth 28
dataAddrWidth 28
tightlyCoupledDataMaster0AddrWidth 1
tightlyCoupledDataMaster1AddrWidth 1
tightlyCoupledDataMaster2AddrWidth 1
tightlyCoupledDataMaster3AddrWidth 1
tightlyCoupledInstructionMaster0AddrWidth 1
tightlyCoupledInstructionMaster1AddrWidth 1
tightlyCoupledInstructionMaster2AddrWidth 1
tightlyCoupledInstructionMaster3AddrWidth 1
instSlaveMapParam <address-map><slave name='Onchip_Memory256KB.s1' start='0x8040000' end='0x8080000' /><slave name='CPU.jtag_debug_module' start='0x8080800' end='0x8081000' /></address-map>
dataSlaveMapParam <address-map><slave name='sdram128MB.s1' start='0x0' end='0x8000000' /><slave name='Onchip_Memory256KB.s1' start='0x8040000' end='0x8080000' /><slave name='CPU.jtag_debug_module' start='0x8080800' end='0x8081000' /><slave name='systimer.s1' start='0x8081000' end='0x8081020' /><slave name='rs232_uart_0.s1' start='0x8081020' end='0x8081040' /><slave name='HEX3TO0PIO.s1' start='0x8081040' end='0x8081050' /><slave name='HEX7TO4PIO.s1' start='0x8081050' end='0x8081060' /><slave name='sd_clk.s1' start='0x8081060' end='0x8081070' /><slave name='sd_wp_n.s1' start='0x8081070' end='0x8081080' /><slave name='sd_cmd.s1' start='0x8081080' end='0x8081090' /><slave name='sd_dat.s1' start='0x8081090' end='0x80810A0' /><slave name='sysid.control_slave' start='0x80810A0' end='0x80810A8' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x80810A8' end='0x80810B0' /><slave name='character_lcd_0.avalon_lcd_slave' start='0x80810B0' end='0x80810B2' /></address-map>
clockFrequency 50000000
deviceFamilyName CYCLONEIVE
internalIrqMaskSystemInfo 7
customInstSlavesSystemInfo <info/>
deviceFeaturesSystemInfo NOT_LISTED 0 INSTALLED 1 IS_DEFAULT_FAMILY 0 ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 IS_CONFIG_ROM 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
tightlyCoupledDataMaster0MapParam
tightlyCoupledDataMaster1MapParam
tightlyCoupledDataMaster2MapParam
tightlyCoupledDataMaster3MapParam
tightlyCoupledInstructionMaster0MapParam
tightlyCoupledInstructionMaster1MapParam
tightlyCoupledInstructionMaster2MapParam
tightlyCoupledInstructionMaster3MapParam
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIG_ENDIAN 0
BREAK_ADDR 0x08080820
CPU_FREQ 50000000u
CPU_ID_SIZE 1
CPU_ID_VALUE 0x00000000
CPU_IMPLEMENTATION "fast"
DATA_ADDR_WIDTH 28
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 2048
EXCEPTION_ADDR 0x08040020
FLUSHDA_SUPPORTED
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
HAS_DEBUG_CORE 1
HAS_DEBUG_STUB
HAS_JMPI_INSTRUCTION
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 4096
INITDA_SUPPORTED
INST_ADDR_WIDTH 28
NUM_OF_SHADOW_REG_SETS 0
RESET_ADDR 0x08040000

Clock_Signals

altera_up_clocks v12.0
clk_0 clk   Clock_Signals
  clk_in_primary
clk_reset  
  clk_in_primary_reset
CPU jtag_debug_module_reset  
  clk_in_primary_reset
sys_clk   CPU
  clk
sys_clk_reset  
  reset_n
sys_clk   Onchip_Memory256KB
  clk1
sys_clk_reset  
  reset1
sys_clk   sysid
  clk
sys_clk_reset  
  reset
sys_clk   systimer
  clk
sys_clk_reset  
  reset
sys_clk   HEX3TO0PIO
  clk
sys_clk_reset  
  reset
sys_clk   character_lcd_0
  clock_reset
sys_clk_reset  
  clock_reset_reset
sys_clk   HEX7TO4PIO
  clk
sys_clk_reset  
  reset
sys_clk   jtag_uart_0
  clk
sys_clk_reset  
  reset
sys_clk   rs232_uart_0
  clk
sys_clk_reset  
  reset
sys_clk_reset   sdram128MB
  reset
sys_clk  
  clk
sys_clk   sd_clk
  clk
sys_clk   sd_wp_n
  clk
sys_clk   sd_cmd
  clk
sys_clk   sd_dat
  clk


Parameters

board DE2-115
sys_clk_freq 50
sdram_clk true
vga_clk false
audio_clk false
audio_clk_freq 12.288
AUTO_CLK_IN_PRIMARY_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY CYCLONEIVE
deviceFamily Cyclone IV E
generateLegacySim false
  

Software Assignments

(none)

sysid

altera_avalon_sysid_qsys v12.0
Clock_Signals sys_clk   sysid
  clk
sys_clk_reset  
  reset
CPU data_master  
  control_slave
jtag_debug_module_reset  
  reset
clk_0 clk_reset  
  reset


Parameters

id 0
timestamp 1411791204
AUTO_CLK_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY CYCLONEIVE
deviceFamily Cyclone IV E
generateLegacySim false
  

Software Assignments

ID 0
TIMESTAMP 1411791204

systimer

altera_avalon_timer v12.0
Clock_Signals sys_clk   systimer
  clk
sys_clk_reset  
  reset
CPU data_master  
  s1
d_irq  
  irq
jtag_debug_module_reset  
  reset
clk_0 clk_reset  
  reset


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
systemFrequency 50000000
timeoutPulseOutput false
timerPreset FULL_FEATURED
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
FIXED_PERIOD 0
SNAPSHOT 1
PERIOD 1
PERIOD_UNITS "ms"
RESET_OUTPUT 0
TIMEOUT_PULSE_OUTPUT 0
FREQ 50000000u
LOAD_VALUE 49999ULL
COUNTER_SIZE 32
MULT 0.0010
TICKS_PER_SEC 1000u

HEX3TO0PIO

altera_avalon_pio v12.0
Clock_Signals sys_clk   HEX3TO0PIO
  clk
sys_clk_reset  
  reset
CPU data_master  
  s1
jtag_debug_module_reset  
  reset
clk_0 clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 50000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 32
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 32
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 50000000u

character_lcd_0

altera_up_avalon_character_lcd v12.0
Clock_Signals sys_clk   character_lcd_0
  clock_reset
sys_clk_reset  
  clock_reset_reset
CPU data_master  
  avalon_lcd_slave
jtag_debug_module_reset  
  clock_reset_reset
clk_0 clk_reset  
  clock_reset_reset


Parameters

cursor Blinking
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY CYCLONEIVE
deviceFamily Cyclone IV E
generateLegacySim false
  

Software Assignments

(none)

HEX7TO4PIO

altera_avalon_pio v12.0
Clock_Signals sys_clk   HEX7TO4PIO
  clk
sys_clk_reset  
  reset
CPU data_master  
  s1
jtag_debug_module_reset  
  reset
clk_0 clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 50000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 32
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 32
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 50000000u

jtag_uart_0

altera_avalon_jtag_uart v12.0
Clock_Signals sys_clk   jtag_uart_0
  clk
sys_clk_reset  
  reset
CPU data_master  
  avalon_jtag_slave
d_irq  
  irq
jtag_debug_module_reset  
  reset
clk_0 clk_reset  
  reset


Parameters

allowMultipleConnections false
avalonSpec 2.0
hubInstanceID 0
legacySignalAllow false
readBufferDepth 64
readIRQThreshold 8
simInputCharacterStream
simInteractiveOptions INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer false
useRegistersForWriteBuffer false
useRelativePathForSimFile false
writeBufferDepth 64
writeIRQThreshold 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

WRITE_DEPTH 64
READ_DEPTH 64
WRITE_THRESHOLD 8
READ_THRESHOLD 8

rs232_uart_0

altera_avalon_uart v12.0
Clock_Signals sys_clk   rs232_uart_0
  clk
sys_clk_reset  
  reset
CPU data_master  
  s1
d_irq  
  irq
jtag_debug_module_reset  
  reset
clk_0 clk_reset  
  reset


Parameters

baud 115200
baudError 0.01
clockRate 50000000
dataBits 8
fixedBaud true
parity NONE
simCharStream
simInteractiveInputEnable false
simInteractiveOutputEnable false
simTrueBaud false
stopBits 1
syncRegDepth 2
useCtsRts true
useEopRegister false
useRelativePathForSimFile false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BAUD 115200
DATA_BITS 8
FIXED_BAUD 1
PARITY 'N'
STOP_BITS 1
SYNC_REG_DEPTH 2
USE_CTS_RTS 1
USE_EOP_REGISTER 0
SIM_TRUE_BAUD 0
SIM_CHAR_STREAM ""
FREQ 50000000u

sdram128MB

altera_avalon_new_sdram_controller v12.0
Clock_Signals sys_clk_reset   sdram128MB
  reset
sys_clk  
  clk
CPU data_master  
  s1
jtag_debug_module_reset  
  reset
clk_0 clk_reset  
  reset


Parameters

TAC 5.5
TMRD 3
TRCD 20.0
TRFC 70.0
TRP 20.0
TWR 14.0
casLatency 3
clockRate 50000000
columnWidth 10
dataWidth 32
generateSimulationModel false
initNOPDelay 0.0
initRefreshCommands 2
masteredTristateBridgeSlave
model custom
numberOfBanks 4
numberOfChipSelects 1
pinsSharedViaTriState false
powerUpDelay 200.0
refreshPeriod 7.8125
registerDataIn true
rowWidth 13
size 134217728
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

REGISTER_DATA_IN 1
SIM_MODEL_BASE 0
SDRAM_DATA_WIDTH 32
SDRAM_ADDR_WIDTH 25
SDRAM_ROW_WIDTH 13
SDRAM_COL_WIDTH 10
SDRAM_NUM_CHIPSELECTS 1
SDRAM_NUM_BANKS 4
REFRESH_PERIOD 7.8125
POWERUP_DELAY 200.0
CAS_LATENCY 3
T_RFC 70.0
T_RP 20.0
T_MRD 3
T_RCD 20.0
T_AC 5.5
T_WR 14.0
INIT_REFRESH_COMMANDS 2
INIT_NOP_DELAY 0.0
SHARED_DATA 0
STARVATION_INDICATOR 0
TRISTATE_BRIDGE_SLAVE ""
IS_INITIALIZED 1
SDRAM_BANK_WIDTH 2
CONTENTS_INFO ""

sd_clk

altera_avalon_pio v12.0
Clock_Signals sys_clk   sd_clk
  clk
clk_0 clk_reset  
  reset
CPU data_master  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 50000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 50000000u

sd_wp_n

altera_avalon_pio v12.0
clk_0 clk_reset   sd_wp_n
  reset
Clock_Signals sys_clk  
  clk
CPU data_master  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 50000000
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 50000000u

sd_cmd

altera_avalon_pio v12.0
clk_0 clk_reset   sd_cmd
  reset
Clock_Signals sys_clk  
  clk
CPU data_master  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 50000000
direction Bidir
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 1
HAS_OUT 0
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 50000000u

sd_dat

altera_avalon_pio v12.0
clk_0 clk_reset   sd_dat
  reset
Clock_Signals sys_clk  
  clk
CPU data_master  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 50000000
direction Bidir
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 1
HAS_OUT 0
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 4
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 50000000u
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