Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2013.2 (lin64) Build 272601 Sat Jun 15 11:11:11 MDT 2013
| Date         : Tue Mar 13 20:43:02 2018
| Host         : predaking running 64-bit Linux Mint 18.2 Sonya
| Command      : report_drc
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Report DRC

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------

REPORT SUMMARY
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
             Checks: defined_DATA_RATE
                     DSP48E1_AregAcascreg
                     Bank IO standard internal Vref conflict
                     Bank IO standard limits
                     Bank IO standard Support
                     Bank IO standard Vcc
                     Bank IO standard Vref utilization
                     Bank IO standard Vref
                     Bank IO standard Termination
                     Input Buffer Connections
                     Missing CFGBVS and CONFIG_VOLTAGE Design Properties
                     Design Rule Check Disabled
                     DCI Cascade IO standard
                     DCI Cascade with part compatibility
                     DCI Cascade Checks
                     Bank IO standard VRN/VRP Occupied
                     Inconsistent Diff pair IOStandards
                     Inconsistent Diff pair IOStandards
                     Inconsistent Diff pair IOStandards
                     DSP48 Buffering
                     DSP48 Cascade
                     DSP input pipelining
                     DSP input registers
                     DSP output pipelining
                     DSP output registers
                     DSP48E1_PregOpmodeZmuxP
                     Cascade input routing
                     Area group tile alignment
                     Pblock overlap
                     Pblock partition
                     FIFO_SynSameClk
                     Reconfigurable cells must have a pblock defined
                     RESET_AFTER_RECONFIG only supported on reconfigurable pblocks
                     Black Box Instances
                     IN_TERM / OUT_TERM requirements
                     IO Bus SLR Crossings
                     Number of IOs
                     IOB clock sharing
                     IOs crosstalk to MGT
                     Directionless IOs
                     Differential IO pads
                     Part compatibility for differing bank types.
                     Incompatible BUFGs among compatible parts.
                     MGT not allowed for part compatibility
                     Part compatibility implied prohibits not respected
                     Part compatibility between monolithic and multi-die devices.
                     IOs placed on disallowed sites
                     IOB set reset sharing
                     IOStandard Type
                     INTERNAL_VREF
                     Longest carry chain height
                     HLUTNM on instances assigned to non-overlapping pblocks
                     LOC Excursion
                     LUTNM on instances assigned to non-overlapping pblocks
                     Combinatorial Loop
                     Bidirection LVDS IOs
                     Multiple Driver Nets
                     No MIG instance
                     Driverless Nets
                     Unspecified I/O Standard
                     defined_IBUF_LOW_PWR
                     connects_TDO
                     Invalid Site Configuration
                     BSCAN_JtagChain
                     Non-Optimal connections to BUFG
                     Unroutable connections to BUFG
                     DRC check of BUFIO loads
                     Clock Placer Checks
                     Placement Constraints Check for Clock Region(s)
                     Design Connectivity Checks
                     Placement Constraints Check for Design Lock
                     DSP Connectivity Checks
                     Unroutable connections to GTH instance
                     Non-Optimal connections which could lead to hold violations
                     IDELAYCTRL DRC Checks
                     IDELAY DRC Checks
                     Dangling IBUFDS output inside IOBUFDS_DIFF_OUT macro 
                     Unroutable connection between IOB and IDDR
                     DRC check between IO and buffer(IBUF/OBUF)
                     IOSTANDARD violations
                     Placement Constraints Check for IO constraints
                     ODELAY Check for 3.3 V standard
                     Inconsistent port properties
                     RAMB output registers
                     connects_I0_connects_I1
                     Unrouted net
                     Missing Site Driver
                     OSERDES driving OBUF
                     Unconstrained Logical Port
                     Resource utilization
                     VCCAUX_IO unsupported with I/O Standard
                     VCCAUX
                     Vccaux voltage requirement for LVCMOS25
                     VCCOSENSEMODE not supported
                     PS7 block required
           Max violations: <unlimited>
         Violations found: 2

2. REPORT DETAILS
-----------------
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties  
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  Refer to the device configuration user guide for more information.
Related violations: <none>

ZPS7-1#1 Warning
PS7 block required  
The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
Related violations: <none>


